1. Field of the Invention
The invention relates in general to logic devices, and more particularly to a fast-switching differential precharge circuit.
2. Description of the Related Art
With the growing complexity of modem computer systems, designers are constantly seeking more efficient methods to reduce power and cost, while increasing speed. Generally, the major components in a computer system are formed from the combination of millions of logic gates. Typically, the power, cost, and speed of the components correlate to the operational efficiency of these logic gates. The switching speed of a logic gate is generally defined in the art as the time that it takes for the output terminal to reflect a change at the input terminal. By significantly improving the performance of the logic gate, the overall performance of the computer system can be improved.
FIG. 1 illustrates six MOS (metal oxide semiconductor) transistors 100, 102, 104, 120, 122, 124 connected to form a conventional static CMOS (complementary MOS) logic gate. The transistors essentially function as switches. These switches are normally open, which prevents current from flowing (i.e., charge from redistributing) and corresponds to the transistor being "off." Transistors can be turned "on" by applying a voltage to an enable input terminal. NMOS transistors are turned "on" when a logically high voltage level is applied to the enable input terminal, while PMOS transistors are turned "on" when a logically low voltage level is applied to the enable input terminal. A logically high voltage level, as defined in this application, is a voltage level that is approximately equal to a reference voltage, while a logically low voltage level is approximately equal to a ground voltage. When a node has a logically high voltage level applied, it is designated as being in a logically "high" state. A node is designated as being in a logically "low" state when a logically low voltage level is applied to the node.
The transistor 100 is a PMOS transistor with an enable input terminal 105 referred to as an input terminal A. When a logically low voltage level is applied to the input terminal A, the transistor 100 turns "on," connecting a reference voltage level V.sub.ref to an output node 110, forcing the output node 110 to a logically "high" state. At approximately the same time, the logically low voltage level at the input terminal A is also applied to an enable input terminal 115 of the is NMOS transistor 120. Thus, the NMOS transistor 120 does not turn "on." One skilled in the art will appreciate that when the input terminals A, B, and C are "high," all of the PMOS transistors 100, 102, 104 in FIG. 1 will be "off," while all of the NMOS transistors 120, 122, 124 will be "on." When any of the input terminals A, B, or C are "low," a logically high voltage level approximately equal to the reference voltage V.sub.ref is present at the output node 110. Similarly, when all of the input terminals A, B, and C are "high," the output node 110 is connected to ground through the transistors 120, 122, 124, and a logically low voltage level is present at the output node 110. The circuit shown in FIG. 1 is configured to implement a logical NAND gate.
Disadvantages of the logic gate of FIG. 1 include the use of several NMOS and PMOS transistors, which generally require a larger surface area. Typically, an increase in the surface area has a corresponding increase in cost. Connection of both NMOS and PMOS transistors may also hinder the switching speed. If, for example, the input terminals A, B, and C were designated as being in the logically "low" state and then changed to the logically "high" state, the PMOS transistors 100, 102, 104 would be turning "off" while the NMOS transistors 120, 122, 124 are turning "on." Generally, it takes longer for the PMOS transistors to turn "off" than it does for the NMOS transistors to turn "on." Thus, there is a period when both the PMOS and the NMOS transistors 100, 102, 104, 120, 122, 124 may be "on," which can delay the output node 110 from achieving the desired state (e.g., a logically "low" state). Also, with all of the transistors 100, 102, 104, 120, 122, 124 turned "on," current flows from V.sub.ref to ground, increasing the power consumed by the static CMOS logic gate.
In this example, the NMOS transistors 120, 122, 124 operate to apply a logically low voltage level at the output node 110, while the PMOS transistors 100, 102, 104 operate to apply a logically high voltage level at the output node 110. Thus, there is a type of "fighting" that may occur between the PMOS transistors 100, 102, 104 and the NMOS transistors 120, 122, 124. In this case, the output node 110 will not fully discharge (i.e., to go to a logically low voltage level) until after all of the PMOS transistors 100, 102, 104 turn "off." This causes a delay between the time the input terminals A, B, and C change and the time the output node 110 reflects the change. This delay results in a decreased switching speed.
FIG. 2A illustrates a conventional, ideal domino logic gate 199, which includes one PMOS transistor 200 and several NMOS transistors 210, 215, 220, 225 serially connected together. A master common clock signal is applied to the enable input terminal of the PMOS transistor 200. When the clock signal is "low" (i.e., has a logically low voltage level), the transistor 200 turns "on," applying a logically high voltage level to an output node 205. The same clock signal is applied to the NMOS transistor 210, which causes the transistor 210 to remain off during the same period. Enabling the PMOS transistor 200 (i.e., turning the PMOS transistor "on"), and disabling the NMOS transistor 210 causes the output node 205 to be in a logically "high" state. Varying the voltage applied to the enable input terminals A, B, and C of the NMOS transistors 215, 220, 225 can cause the output node 205 to discharge (i.e., go to a logically "low" state). For example, if the input terminals A, B, and C are all at a logically high voltage level while the clock signal is at a logically high voltage level, such that all of the NMOS transistors 210, 215, 220, 225 are turned "on," then the output node 205 will discharge. The logic gate 199 shown in FIG. 2A is configured to implement a logical NAND gate.
Problems with the circuit of FIG. 2A include charge-sharing, which can cause an incorrect state at the output node 205. For example, if the input terminal A and input terminal B are "high," the transistors 215 and 220 would be "on." Thus, some of the charge present at the output node 205 can be redistributed to intermediate nodes 216 and 230. The charge shift to the intermediate nodes 216 and 230 can cause the voltage level present at the output node 205 to drop substantially, causing the logically high voltage level to be seen as a logically low voltage level. This can cause the logic gate 199 to function improperly.
FIG. 2B illustrates a modified domino logic gate 231, which includes an additional PMOS transistor 235 and an inverter 240. The enable input terminal of the PMOS transistor 235 is connected to the output terminal of the inverter 240. When the voltage level of the clock is "low," the output node 205 is at a logically high voltage level, which causes the output terminal of the inverter 240 to be at a logically low voltage level. The logically low voltage level from the inverter 240 is applied to the enable input terminal of the PMOS transistor 235, which causes that transistor 235 to turn "on." When the transistor 235 is "on," it helps to maintain a high voltage level at the output node 205. The logic gate 231 shown in FIG. 2B is configured to implement a logical NAND gate.
If the input terminals A, B, and C have a high voltage level applied, the NMOS transistors 215, 220, 225 apply a logically low voltage to the output node 205, while the PMOS transistor 235 applies a logically high voltage. The output node 205 cannot fully discharge until the PMOS transistor 235 turns "off," which causes a delay and limits the switching speed of the logic gate 231. In addition, during this period where both the PMOS and NMOS transistors 235, 215, 220, 225, 210 are "on," wasted current flows from V.sub.ref to ground. Moreover, the logic gate 231 of FIG. 2B still has a similar potential for charge-sharing as described in conjunction with the logic gate 199 of FIG. 2A.
FIG. 3 shows a conventional Cascode Voltage Switch Logic (CVSL) gate 300, which may function similarly to two domino gates. One side of the gate 300 charges while the other side of the gate 300 discharges. CVSL is known in the art as a dual-rail structure. This type of structure employs an inverted input terminal for each input terminal. Thus, in FIG. 3 input terminals A-F have corresponding inverted input terminals A.sup.# -F.sup.#. Generally, a dual-rail structure employs a larger area and more power. In addition, CVSL may also have "fighting" during the discharge cycle, which can cause the switching speed to be limited. If sense amplifiers are placed on both out and out.sup.# nodes to achieve more sensitive detection, noise present at either the out or out.sup.# nodes will also be amplified, which can cause the gate to malfunction. Thus, it would be beneficial to have a differential precharge circuit that is capable of overcoming the shortcomings of conventional structures and methods.